At LeanRISC, we have collaborated with various customers to verify complex SoC designs. Our experience runs deep and our expertise includes:
RTL simulations are giving way to Transaction Level Modeling for more and more modern SoC projects. For one, RTL simulators have not been able to keep up on simulation speed requirements for growing complexity of the designs. Another factor contributing to the trend is the need for hardware software coverification. At LeanRISC our approach towards ESL modeling is multipronged:
With the intricate binding between the Hardware and Software, it is becoming increasingly difficult to verify them in isolation. Over the last couple of years, LeanRISC has pioneered techniques to translate software interactions with hardware into TLM transactions that drive stimulus into a hardware testbench simulation. These techniques can help you validate your device drivers early in the design cycle and also make sure that your hardware design is compatible with software. Software Driven Verification provides you with:
Field Programmable Gate Arrays are considered a primary technology driver for the Internet of Things domain. Given the intricately heterogenous nature of the IoT devices, a comprehensive verification solution for IoT devices has to include in-system testing of the FPGA devices. Embedded FPGA verification enables:
A definitive verification like the UVM is necessary to accelerate verification productivity and enable reuse. Scripting and automation, on the other hand, are required to gain consistecy and mitigate the risk of human errors. Besides, UVM is not a one size fits all solution, the vagaries and variations of the design require custom tailor made solutions. LeanRISC can help you with: