Hardware Design Verification

At LeanRISC, we have collaborated with various customers to verify complex SoC designs. Our experience runs deep and our expertise includes:

  1. Creating SystemVerilog/UVM powered custom Verification IP
  2. Integrating UVM compliant testbench infrastructure
  3. Writing reference models in C/C++ to verify the design functionality using DPI layer
  4. Wide domain expertize including Ethernet, Telecom, Automobile, Network-on-Chip, HDMI, PCI-Express and USB protocols
  5. We also provide corporate trainings for SystemVerilog and UVM, as part of bootstrapping verification effort at customer site

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System Modeling

RTL simulations are giving way to Transaction Level Modeling for more and more modern SoC projects. For one, RTL simulators have not been able to keep up on simulation speed requirements for growing complexity of the designs. Another factor contributing to the trend is the need for hardware software coverification. At LeanRISC our approach towards ESL modeling is multipronged:

  1. We have learnt to take advantage of multicore programming to accelerate behavioral simulations
  2. We excel in integrating various simulation tools and flows across the spectrum of varied abstraction levels
  3. For testbenching System Level simulations, we have mastered the art of integrating SystemVerilog with C++ using DPI layer
  4. Alternatively, we can help create SystemC-UVM powered testbench

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Software Driven Verification

With the intricate binding between the Hardware and Software, it is becoming increasingly difficult to verify them in isolation. Over the last couple of years, LeanRISC has pioneered techniques to translate software interactions with hardware into TLM transactions that drive stimulus into a hardware testbench simulation. These techniques can help you validate your device drivers early in the design cycle and also make sure that your hardware design is compatible with software. Software Driven Verification provides you with:

  1. A software development platform, complete with device drivers and application software
  2. The device driver and the application executes in a caged emulation environment such as Qemu
  3. A C++ DPI layer interfaces the software environment with testbench coded in SystemVerilog
  4. A C++ reference model that integrates with the testbench or alternatively as a software model for the development environment

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FPGA Prototyping/Emulation

Field Programmable Gate Arrays are considered a primary technology driver for the Internet of Things domain. Given the intricately heterogenous nature of the IoT devices, a comprehensive verification solution for IoT devices has to include in-system testing of the FPGA devices. Embedded FPGA verification enables:

  1. Coverification of sensors and other analog portions of the IoT device.
  2. An efficient verification environment, fast enough to provide a viable software development environment
  3. Reuse of UVM-based verification environment
  4. Note that LeanRISC provides custom emulation solutions that are cost effective

Take a look at Vlang/Qemu interface demo Back to Top

Scripting and Automation

A definitive verification like the UVM is necessary to accelerate verification productivity and enable reuse. Scripting and automation, on the other hand, are required to gain consistecy and mitigate the risk of human errors. Besides, UVM is not a one size fits all solution, the vagaries and variations of the design require custom tailor made solutions. LeanRISC can help you with:

  1. PLI based design introspection that can ensure consitency in the RTL design and/or UVM testbench
  2. Scripts based custom solutiond to analyze the dumped waveforms

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